SPEAr1340 Embedded Dual-Core ARM Cortex-A9 Processors. Beijing collapses Wall Street

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Main settings

general description

The internal architecture of SPEA-1340 is based on several shared subsystem logic blocks that interact through a multi-level switching matrix (BUSMATRIX). The structure of the multi-level matrix allows data exchange between subsystem units in parallel, which increases the overall performance of the platform. High-performance master agents are directly connected to the memory controller, thereby reducing access times. The total memory bandwidth assigned to each master port can be programmatically tuned and optimized through an internal weighted round-robin arbitration scheme.

Distinctive features:

• Central processing unit
  • Dual ARM Cortex A9 cores up to 600 MHz
  • Supports symmetric (SMP) and asymmetric (AMP) multiprocessor computing
  • 32KB Instruction Cache and 32KB L1 Data Cache with Parity
  • 512KB shared L2 cache with ECC and parity
  • Asynchronous Data Integrity Controller (ACP) Port
  • Bus: 64-bit network-on-a-chip multilayer
• Memory
  • 32KB boot memory
  • 32KB + 4KB internal RAM
  • DDR2-800 / DDR3-1066 Multiport External Memory Controller (MPMC) with 16- / 32-bit data path, address space up to 1 GB with single / double error correction code
  • Controller (FSMC) for external NAND FLASH, parallel NOR FLASH and asynchronous SRAM
  • Controller (SMI) of serial NOR FLASH memory
• Communication interfaces
  • Gigabit / Fast Ethernet port (with external physical layer GMII / RGMII / MII)
  • PCIe 2.0 RC / EP Port (Onboard PHY)
  • SATA Gen. Host Port 2 (as an alternative to PCIe bus)
  • Two USB 2.0 Host ports with integrated physical layer
  • USB 2.0 OTG port with integrated physical layer
  • Two UART channels (baud rate up to 5 Mbaud), IrDA compatible
  • SSP port (support SPI and other protocols), master / slave mode, speed up to 41 Mbaud
  • Two I 2 C ports with master / slave mode
  • Memory Card Interface (MCIF)
  • Touchscreen interface (4-wire, resistive)
  • 6x6 keyboard controller
  • Two CEC (Consumer Electronic ontrol) interface ports
  • Audio: multichannel 7.1 sound: two I 2 S ports (8 input + 8 output channels), S / PDIF interface
• Video
  • TFT LCD controller with resolution up to 1920x1200 pixels (60 Hz), 24 bits per pixel
  • High-performance MALI200 GPU with 2D / 3D graphics, 1080p resolution, support for OpenGL ES 2.0, OpenVG 2.0
  • High Definition Video Decoder, up to 1080p: Supports compression standards H263, H264, MPEG2, MPEG4, VC1, Sorenson Spark, AVS, VPS 6-7-8, RealVideo, DivX, JPEG (67 Megapixels)
  • High-definition video encoder, resolution up to 1080p: supports compression standards H264, JPEG (67 Megapixels)
  • Alternatively configured digital video input port for four camera inputs
• Additional features
  • Two high performance 8-channel Direct Memory Access Controllers (DMAC)
  • Four PWM generators
  • 10-bit ADC, speed up to 1 MSPS (Msamples per second), 8 channels with autoscan function
  • General Purpose Programmable Bidirectional I / O (GPIO) with Interrupt Function
  • Security: C3 cryptographic accelerator
  • Thirteen timers and real time clock
  • 510 + 209 once programmable bits
  • Built-in junction temperature monitoring sensor
  • JTAG-PTM debug and test interface
  • Various low power modes
• Typical Power Consumption: 2.5W
• Operating temperature range: -40 ... + 85 ° C

For over a decade, ARM solutions have dominated the mobile market. They are currently used in more than 90 percent of portable devices, thanks to the incredible rise in popularity of smartphones. Starting with the microarchitecture ARMv7 and the first processor based on it, the A8 processor, which later reached the frequency barrier of 1 GHz, smartphones rightfully began to be called mini-computers.

Then came the dual-core Cortex A9 chips, equipped with a powerful graphics core capable of rendering high-quality images, which 6-7 years ago were available only for PCs. Today, the Cortex A9 processors are being replaced by a new generation of mobile Cortex A15 processors, designed to further reduce the computing distance between mobile devices and PCs.

Performance

Speaking of computational capabilities, it is worth looking at the DMIPS / MHz ratio parameter, which, although indirectly, can still be used to evaluate performance. So, for Cortex A9 it is 2.5, and in the case of Cortex A15, the DMIPS / MHz ratio is expected to be 3.5, moreover, some manufacturers promise to raise it to 4.0.

Reference: DMIPS shows how many million instructions the processor can execute in the Dhrystone benchmark per second.

Thus, one can expect a performance gain of 40-60 percent, but here one should take into account the difference in the clock frequency of the processors. For example, a 2GHz dual-core Cortex A15 chip like the upcoming Exynos 5250 should run twice as fast as a 1.5GHz dual-core Cortex A9 solution, and that's only in the case of a single thread.

Also keep in mind that in the case of multi-threaded performance, doubling the number of cores obviously does not double the performance. According to experts, dual-core Cortex A15 chips will perform on average 30 percent faster than modern quad-core mobile solutions.

New opportunities

Unlike Cortex A9, whose frequency reserve was limited to 2 GHz per core, in Cortex A15 this parameter will grow to 2.5 GHz, and the possible number of cores will increase from 4 to 8 by the middle of 2013.

It is also worth paying attention to the NEON support built into the Cortex A15, the ability to work with up to 1 TB of RAM and hardware virtualization functions, which will certainly appeal to fans of installing alternative firmware.

Graphics core

The first chipset based on the Cortex A15 processor should be Samsung's Exynos 5250, which should appear next summer or early fall. Most likely, the novelty will act as a hardware basis for a Google tablet, which is expected to be announced at the Google I / O conference.

The new chipset will include the Mali T-604 graphics core, which will be the most powerful graphics solution in the mobile industry this year. The performance of the T-604 will be double that of the Adreno 225 and even better than that of the Adreno 320. Compared to the previous version of the Mali 400 graphics core (used in the Galaxy S2), a five-fold increase in performance is expected.

In addition, the new graphics engine will support Google's Renderscript in hardware for rendering the Android 4.0 UI and the OpenCL instruction set.

Big.Little

The plans for the Cortex A15 from various manufacturers are quite extensive. So Samsung plans to use this particular architecture to create a hardware platform for the new smartphone of the Nexus line, and it is not at all necessary that the Exynos 5250 will be used as the chipset. Most likely, the new Googlephone will be based on a solution built using big.Little technology with a special Cortex A7 core. used for current calculations.

Cortex A7 chips themselves, designed to replace outdated ARM11 solutions in the future, may turn out to be no less interesting. According to experts, the new chips will significantly revive the segment of low-cost Android solutions costing up to $ 100.

Perspectives

Despite the full potential of Cortex A15, Mali T-604 and Cortex A7, they are already being replaced by 64-bit solutions based on the ARMv8 microarchitecture, which should appear in 2014. However, no one guarantees support for such solutions from software developers, as it happened with 64-bit processors from Intel and AMD.

What ARMv8 will bring to the Android platform remains to be seen, but the Linux community is already looking with enthusiasm towards 64-bit chips.