Memory controllers can protect the pc's memory. Dynamic memory controller Writing data to the memory chip

Any flash memory is based on a silicon crystal on which not quite ordinary field-effect transistors are formed. Such a transistor has two isolated gates: control and floating. The latter is able to hold electrons, that is, charge. The cell, like any field-effect transistor, has a drain and a source (fig. 4.1). During the recording process, a positive voltage is applied to the control gate, and some of the electrons moving from the drain to the source are deflected towards the floating gate. Some of the electrons pass through the insulator layer and diffuse into the floating gate. They can stay in it for many years.

The concentration of electrons in the area of \u200b\u200bthe floating gate determines one of the two stable states of the transistor - the memory cell. In the first, initial state, the number of electrons on the floating gate is small, and the threshold voltage for opening the transistor is relatively low (logical unit). When enough electrons are brought into the floating gate, the transistor is in a second steady state. Its opening voltage increases sharply, which corresponds to a logical zero. When reading is measured

Figure: 4.1. Flash memory cell

the threshold voltage that must be applied to the drain to open the transistor. To remove information, a negative voltage is briefly applied to the control gate, and electrons from the floating gate diffuse back to the source. The transistor again goes into the state of a logical unit and remains in it until the next write is made. It is noteworthy that in flash memory one transistor stores one bit of information - it is a cell. The whole process of "memorization" is based on the diffusion of electrons in a semiconductor. This leads to two not very optimistic conclusions.

The storage time of the charge is very long and is measured in years, but still limited. The laws of thermodynamics and diffusion state that the concentration of electrons in different regions will sooner or later equalize.

For the same reason, the number of write-rewrite cycles is limited: from one hundred thousand to several million. Over time, degradation of the material itself and pn-junctions inevitably occurs. For example, Kingston Compact Flash cards are rated for 300,000 rewrite cycles. Transcend Compact Flash - on

1 LLC, and the Transcend 32 Gb USB flash drive - for only 100 LLC.

There are two flash architectures. They differ in the way they refer to the cells and, accordingly, in the organization of the internal conductors.

NOR memory allows you to access cells one at a time. Each cell has a separate conductor. The NOR memory address space allows you to work with individual bytes or words (each word contains

2 bytes). This architecture imposes serious restrictions on the maximum amount of memory per unit of die area. NOR memory is currently only used in BIOS chips and other low-capacity ROMs such as cell phones.

In NAND (NAND) memory, each cell is at the intersection of a "bit line" and a "word line". Cells are grouped into small blocks similar to a cluster hard disk... Both reading and writing are carried out only in whole blocks or lines. All modern removable media are built on NAND memory.

The largest manufacturers of NAND chips are Intel, Micron Technology, Sony and Samsung. The range of manufactured chips is quite large, and it is updated several times a year.

Controllers

A memory controller is used to control reading and writing. Currently, the controller is always executed as individual element (this is either a microcircuit of one of the standard form factors, or an unpackaged chip built into a memory card), although work is underway to integrate the controller directly into the flash memory crystal.

Controllers are designed and produced for completely specific flash memory chips. The way of addressing cells is structurally incorporated in the controller. When written to a flash memory chip, data is arranged in a specific way that varies from model to model. The manufacturers keep these details a secret and, apparently, do not plan to disclose. Obviously, much more controller firmware is created than controller models themselves. The controller firmware (firmware) and the address translation table (translator) are written into the service area of \u200b\u200bthe flash memory. It is this area that the controller begins to read immediately after power is applied to it. In addition to the actual addressing of cells, the controller performs a number of other functions: the functions of monitoring bad sectors, error correction (ECC - error check and correct) and uniformity of cell wear (wear leveling).

The technological norm in the manufacture of memory microcircuits is the presence in them on average up to 2% of non-working cells. Over time, their number may increase, therefore, as in hard drives, a reserve volume is provided in the flash memory. If a defective sector appears, the controller replaces its address in the file allocation table with the sector address from the spare area during formatting or writing. The correction is carried out by the controller, but is implemented at the level of the file system of a particular media.

Due to the limited resource of the cells (on the order of several million read / write cycles for each), the controller has a function of accounting for the uniformity of wear. In order to record information evenly, free space is conventionally divided into sections, and for each of them the number of write operations is taken into account. Cycle statistics are stored in a hidden service area of \u200b\u200bmemory, and the controller periodically refers to it for this information. This does not affect addressing.

USB flash disk design

Despite the variety of enclosures, all USB flash drives have the same structure. If the halves of the case are connected by snaps, they usually separate easily. Housings that are waterproof or trendy have to be opened with destructive methods, such as cutting.

There are two microcircuits on the board inside the USB flash disk (Fig. 4.2): a memory chip and a controller. Both have factory markings. Sometimes the board carries two flash memory chips that work in pairs. The microcircuit harness consists of several resistors and diodes, a power stabilizer and a quartz resonator. Recently, the stabilizer is increasingly being built directly into the controller and the number of attachments has been reduced to a minimum. In addition, the board may contain an LED indicator and a write-protect miniature switch.

Figure: 4.2. Flash disk device

The USB connector is soldered directly to the board. The soldering points of the contacts in many models are quite vulnerable, since they bear the mechanical load when connecting and disconnecting the device.

Types and design of memory cards

Many companies from time to time offered users different designs of memory cards. With rare exceptions, they are all incompatible with each other in terms of the number and location of contacts and electrical characteristicsFlash cards are of two types: parallel and serial interfaces.

Table 4.1 lists the 12 main types of memory cards that are currently found. Within each type there are additional varieties, taking into account which we can talk about the existence of almost 40 types of cards.

Table 4.1. Types of memory cards

Memory card type	Overall dimensions, mm)	Maximum constructive	Interface
CompactFlash (CF)			Parallel 50 pins
			Serial 9 pins
MultiMedia Card (MMS)			Serial 7 pins
			Serial 7 pins
Highspeed MMS			Serial 13 pins
			Serial 10 pins
Memory Stick PRO			Serial 10 pins
Memory Stick Duo			Serial 10 pins
SmartMedia (SSFDC)			Parallel 22 pins
			Parallel 22 pins
			Serial 8 pins

MMC cards can work in two modes: MMC (MultiMedia Card) and SPI (Serial Peripheral Interface). The SPI mode is part of the MMC protocol and is used when communicating with the SPI channel in microcontrollers from Motorola and some other manufacturers.

An MMC (MultiMedia Card) card can be inserted into the SD (Secure Digital) card slot, but not vice versa. The SD card controller contains hardware data encryption, and the memory itself is equipped with a special area in which the encryption key is stored. This was done in order to prevent illegal copying of music records, for the storage and sale of which such a medium was intended. The card has a write protection switch.

CompactFlash (CF) cards can easily be inserted into the Type II PCMCIA slot. Despite the fact that PCMCIA has 68 pins and CF has only 50, the CompactFlash cards are designed for full compatibility and have all the functionality of the PCMCIA-AT A format.

All Maps memory Memory Stick (Sony Corporation standard) are relatively compatible with each other. The standard theoretically provides for a memory card capacity of up to 2 TB, although in reality the capacity reaches units of gigabytes.

SmartMedia cards are largely obsolete and can only be found in very old digital cameras. It is noteworthy that this was the only standard in which the controller was not inside the card, but in the reader.

The construction of memory cards is non-separable - this is a device not suitable for repair. Unpackaged microcircuits together with the leads are molded into a compound and all together are pressed into a plastic shell. You can get to the crystal only by opening the device, but damage to the conductors is almost inevitable.

Readers

To read a USB flash disk, a regular uSB port: The computer sees such devices as a standard removable disk thanks to their controller. The controllers of all memory cards are directed to the computer by serial or parallel interfaces - contacts on the card. For each of these interfaces, a corresponding adapter is needed - an additional controller that matches this interface with standard port USB.

Card reader is a device consisting of one or more similar controllers, a power converter and connectors for different cards memory (fig. 4.3). Power is supplied from a +5 V source via a USB cable.

Figure: 4.3. Card reader

Most often there are "combines" designed for several types of cards: from 6 to 40. There are much fewer slots in the card reader, since each slot is used for several types of cards that are close in size and contact arrangement. In terms of their characteristics, different models are practically equal, but differ mainly in the number of supported card types and design.

Logical organization

Before moving on to flash drive file systems, you need to think about the NAND architecture. In this frequently used memory, reading, writing and deleting information occurs only in blocks.

On hard and floppy disks, the block size is 512 bytes, excluding 59 overhead bytes, which are visible only to the hard drive controller. All file systems were created with these values \u200b\u200bin mind. The problem is that in flash memory the size of the erase block, with rare exceptions, does not match the size of a standard disk sector of 512 bytes and is usually 4.8 or even 64 KB. On the other hand, the read / write block must match the size of the disk sector to ensure compatibility.

To do this, the erasure block is divided into several read / write blocks with a size of 512 bytes. In practice, the block is slightly larger: in addition to 512 bytes for data, it also has a 16-byte Tail for service information about the block itself. Physically, the location and number of read / write units are not limited by anything. The only limitation is that the read / write block must not cross the boundary of the erase block, since it cannot belong to two different erase blocks.

Read / write blocks are divided into three types: valid, invalid, and defective. Blocks that contain written data and belong to a file are valid. Used blocks with outdated information are considered invalid and must be cleaned up. The defective category is made up of blocks that cannot be written and erased.

Another feature of flash memory is that information can only be written to the space previously cleared of previous information. When information needs to be written, the controller firmware must decide which invalid blocks to erase before doing so. In the majority of microprograms, the issue of deleting invalid blocks is solved in the simplest way: as soon as a certain part of the capacity of the flash disk is filled with information, the mechanism for clearing invalid blocks is automatically started.

To extend memory lifespan, wear-leveling control technology is used, which prolongs life cycle memory crystal due to uniform distribution of write / erase cycles of memory blocks. A side effect - failure of one memory block - does not affect the operation of other memory blocks of the same crystal. Fixed blocks belong to files that have never changed or moved for a long time or at all. The presence of stationary data blocks leads to the fact that the remaining part of the cells is subject to increased wear and more quickly depletes its resource. The firmware takes into account such blocks and moves their contents to other cells as necessary.

At first glance, the file systems of flash disks and memory cards are well known to users from hard and floppy disks. This is FAT16, less often FAT32: this is how the Windows operating system suggests formatting a disk. Standard windows tools XP and Windows 7, the disk can be formatted in nTFS system! To do this, first go to the Device Manager and in the properties window of the connected flash drive on the Policy tab select the Optimization for fast execution value. Special programs from manufacturers, such as the HP USB Disk Storage Format Tool, allow you to format flash drives to NTFS without that effort.

However, the external similarity of file systems solid state drives and ordinary hard drives are deceptive. Flash file system (Flash File System, FFS) only emulates a regular disk drive and consists of control blocks and an initialization block. In fact, only the controller of the flash disk or memory card knows about the true location and addressing of memory blocks.

This is very important for different methods of restoring the contents of a flash memory chip. When a memory chip is read through its "native" controller, the image file contains a sequence of blocks in the order of their numbers or offsets. At the beginning are the header and the file system table. If the reading is performed on the programmer, service information is located in the initial blocks of the dump, and the blocks with the data are mixed almost randomly. At the same time, the service information is unlikely to be useful, since it entirely depends on the controller model and its firmware - the correct sequence of blocks has to be compiled with great difficulty.

Some cameras work only with the RAW file system. The method of recording photographs on a medium with such a file system, as well as the specifics of formatting the card itself, depend on the model of the device and even the firmware of one model or another. This format is not standardized and has many variations. Usually, data from such cards can only be restored by service programs from the manufacturer of the camera, and it is advisable to use the camera itself as a card reader.

Figure: 4.4. Format flash disk window Windows Vista SPl

The innovation is file system exFAT (Extended FAT - extended FAT). Support for this specially designed file system for flash drives was first introduced with Windows Embedded CE 6.0. Windows Vista Service Pack 1 and Windows 7 work with exFAT (Figure 4.4).

The purpose of the new file system is to gradually replace FAT and FAT32 on flash drives. It contains some features that were previously only inherent in the NTFS file system:

The 4 GB file size limit has been overcome: the theoretical limit is 2 ^ bytes (16 exabytes);

Improved allocation of free space by introducing a bitmap of free space, which reduces disk fragmentation;

The limit on the number of files in one directory has been removed;

Added support for access rights list.

How soon this file system will become the norm for flash drives, time will tell. Apparently, this will not happen earlier than at operating system Windows 7 will go over the vast majority of users.

As an example of the implementation of the principles of direct memory access (DMA), consider the KR580VT57 microcircuit. The programmable DPS controller is designed for high-speed data exchange between the system memory and four external devices (VU).

The controller carries out a bi-directional data exchange between the memory and the VU (at the request of the VU), while in the address channel of the microprocessor system, the parameters of a given array of addresses of memory cells (starting address and number of cycles) and control signals are formed. Each of the four channels of the controller provides addressing (by incrementing the generated address) of external memory in arrays of up to 16K bytes with the ability to set any of 64K starting addresses.

The composition of the PDP controller

The following blocks can be distinguished in the controller (Fig. 3.11.1): a request processing block, an address generator, a read-write logic block, a control block, a data buffer and two registers - a mode setting register and a channel status register. Let's consider their features.

The request processing block is intended:

● for receptionsignals of request ZPDP0 – ZPDP3 for direct access to memory from VU;

● for maskingchannel inputs K0 – K3;

● for issuingconfirmation signals of the request ¯PPDT0 - ¯PPPP3 of direct memory access, informing the VU about the readiness of the controller to exchange data via the DPS channel.

The address generator contains 16-bit registers of the initial address (PHA0… PHA3) and the number of cycles (RFC0… RFC3), an increment-decrement circuit, a trigger. During the execution of the initial setup program, the initial address of the memory cell is written into the PHA, which will be accessed by the VU via the DMA channel. In the 14 least significant bits of the register of the number of RFC cycles, the number N - 1 is entered, where N is the number of cycles. The two most significant bits of this register are used to control the exchange over the DMA channel.

In each cycle, two address bytes are read from the PHA. The trigger provides the order of reading: the high byte is output through the data buffer to the stepper motor, and the low byte of the address - via the buses A0 ... A3, A4 ... A7. At the end of the cycle, the increment – \u200b\u200bdecrement scheme increases the PHA content and decreases the RFC content by one. It should be noted that the controller outputs A4 ... A7 are always used as outputs for the A4 ... A7 bits of the address code, and the outputs A0 ... A3 are used:

• as outputsfor transmission of the least significant bits of the address code during the operation of the PDP channel;
• as entrancesto select the register with which the information will be exchanged. This need arises when writing the initial setup program to the PDP controller, as well as when reading the contents of the address register, the number of cycles register or the status register.

Read-write logic block

receives, generates and outputs signals that provide information exchange between the processor and the controller of the PDP, memory and VU. The read-write logic block has the following outputs:

● ¯Зп - bi-directional control three-stable input / output used:

how entrance forreceiving signal from processor to recordingdata into the internal registers of the PDP controller during its initial installation;

how output,on which a signal is generated allowing an external device recordingdata from memory;

● ¯Fr - bi-directional three-stable control input / output used:

how entranceto receive a signal from the processor allowing reading(output) the contents of the internal registers of the controller;

how outlet forissuing a signal for permission readoutsdata from WU to memory;

● ¯ЧтП, ¯ЗпП - outputs for control of reading from memory and writing to memory;

● ¯VK - input (crystal selection), to which the zero chip select signal is applied after the write or read signals are set. Signal ¯ВК initiates data exchange between the processor and the internal registers of the PDP controller during programming; automatically locked in direct access mode. The ¯VK input is connected to the SHA of the microprocessor system directly or through a decoder.

The ¯Zp, ¯Cht pins are connected to the processor as inputs and to the WU as outputs, and the ¯ZpP, ¯ChtP outputs are connected to the memory of the microprocessor system.

At the stage initial setupthe lower-order bits A3 ... A0 of the address code are decrypted in the address generator, and after the signals ¯Зп, ¯Тт are received from the processor, writing or reading of the programmable registers of the PDP device is organized. When working in a loopPDP logical circuits of the read-write unit form pairs of signals ¯Cht, ¯ZpP and ¯Zp, ¯ChtP at the outputs of the device, providing clocking of the data exchange process between the WU and the memory.

Control block

regulates the sequence of operations during all DAP cycles using control signals, and also transfers the controller from the standby state to the service state by the capture confirmation signal (PZx). The control unit has the following leads:

• ЗЗх (Н RQ) - the output from which the signal is taken capture requestfor microprocessor;
• ПЗх (HLDA) - the input to which the signal is received capture confirmationfrom a microprocessor;
• GT (RDY) - control input readiness.The signal Гт \u003d 1 from the VU activates the operation of the PDP controller; signal Гт \u003d 0 transfers the controller to the standby state;
• М128 - exit 128th cycle marker:M128 \u003d 1 indicates that the current DPS cycle is the 128th cycle from the end of the data array;
• KS (TS) - exit end of account:KS \u003d 1 indicates to the VU that the current exchange cycle on the PDP channel is the last one when transmitting the data array. If the "КС-stop" bit in the mode setting register is set to 1, then the channel will be disabled. The KS output is activated (KS \u003d 1) when the contents of the 14-bit register of the number of cycles in this channel is set to 0;
• RA (AE) - exit address permissions:PA \u003d 1 indicates to the system that direct access cycles are occurring. In this case, all buses are disconnected from the microprocessor. The signal can be used to block the address bus in devices that do not participate in direct access, as well as to write the high-order eight bits of the address code into the buffer address register and disable the device's sampling circuit. In the DPS mode, the device is sampled by the signals ¯PPDT0 - ¯PPDT3;
• StA (STBA) - exit address strobe,the signal of which strobes the high byte of the memory address, transmitted through the SM to the additional data buffer. Through this buffer, the most significant byte of the address goes to the address bus of the microprocessor system;
• TI - input for clock pulses;
• Reset - enter the initial setting of the device. Applying a single signal to this input clears the contents of all software available registers, which disables channels K0 - K3.

The data buffer is an 8-bit bidirectional three-state bus connecting the DMA controller with the system data bus of the SM.

Via data buffer:

• at programmingin the write mode, eight data bits D 7 ... D 0 from the microprocessor are transferred to the DMA controller for writing to the starting address register, the cycle number register or the mode setting register; when the processor reads from the PDP device, the contents of the initial address register, the number of cycles register and the channel status register are displayed;
• at channel workDMA at the beginning of each cycle, the most significant eight bits of the address are transferred from the address register of the corresponding channel to memory. Then the stepper motor is released for direct data exchange between the memory and the VU during the rest of the cycle. This data does not pass through the PDP device.

Installation register

modes stores information about the programmed modes of autoload, extended and normal recording, fixed priority and cyclic priority shift, KS-stop, etc. An 8-bit control word is written into it when programming the PDP controller. The mode setting register is usually loaded after the address register(PrA) and loop register(RgTs). The purpose of the bits of the mode setting register is shown in Table. 3.11.1.

Channel status register

indicates in which of the four channels the process of transferring the array ended. To do this, the value of the signal KS \u003d 1 of the end of the count appearing at the output of the KS and indicating the end of the array via the corresponding channel is written in the least significant bits of the PC0 – PC3 (flags of service completion). Assigning digits mode setting registeris given in table. 3.11.2.

Basic states and operating modes of the device.

The main states are initial state, programming, waiting and service.

The initial state.

Upon entering the entrance Reseta single signal, the device goes into initialstate. In this state, the requests of all DMA channels are masked (P0 \u003d P1 \u003d P2 \u003d P3 \u003d 0), the buffer circuits of the bus A0 ... A3 are transferred to the state of receiving information.

Programming.

Capable of programmingdevice microprocessor on the data bus (ШД - D 0 ... D 7) writes the starting address, the number of cycles and other data into the corresponding registers, the address of which is set by the code А 3 А 2 А 1 А 0 on buses А0 – А3 (Table 3.11. 3). The most significant bit of the A3 code allows you to distinguish when A3 \u003d 0 - channel registersK0 ... K3; at A3 \u003d 1 - mode setting register(works only for writing) and channel status register(works only for reading). The least significant bit A0 selects the registers of the initial address (A0 \u003d 0) and the number of cycles (A0 \u003d 1). The two middle digits A 2 A 1 indicate the numbers of registers (or channels) in binary code. For example, code 0101 corresponds to RFC2 - the register of the number of cycles of channel 2. Registers of the PDP controller are loaded or information is read from them if the microprocessor executes a write or read command by accessing the device and its registers. To do this, the microprocessor needs to issue the appropriate write signals ¯Зп or read ¯Пт and set the register address in the form of the code А 3 А 2 А 1 А 0 on the system address buses ША. At this time, the necessary information D 7 ... D 0 is supplied to the SM data bus to write to the registers or information from the PDP controller is read through the SM data bus. To set the programming state, it is also necessary to send the device sampling signal ¯ВК \u003d 0. Since the channel registers are 16-bit, two program command cycles are required to load or read them. IN address generatorthe controller has a trigger that automatically switches circuits during read or write operations. This trigger determines the access to the high or low bytes of the register. The trigger is reset by applying a single signal to the input Reset,and also whenever the mode setting register is loaded.

To ensure proper synchronization when accessing the channel registers, all commands must come from the microprocessor in pairs, there must be no gaps between them.

Expectation.

Capable of expectationsthe controller receives from the WU a signal of a request to receive a DPS cycle (DPS0 – DPS3) and generates a capture request signal (ZZx) for the microprocessor. In this state, the system buses are controlled by the microprocessor.

Service.

After receiving a capture confirmation signal from the microprocessor (PZx), in the presence of a request signal (ZPDP0 - ZPDP3) from the WU, the controller generates a request confirmation signal (¯PPADP0 - ¯PPDP3) for one of the WU and goes to service status. INin this state, the system buses are under the control of the controller, and one of the programmed DMA modes is implemented:

• the lower 8 bits of the memory address go to the buses A0 – A3, A4 – A7, the higher 8 bits - to the data bus of the SM;
• corresponding control signals ¯ChTP and ¯ZpP, ¯Zp and ¯Cht are formed, which allow the VU to receive from a memory cell or transfer to a memory cell in one data byte cycle.

In the first cycle of operation, the DMA device transmits the starting address of the memory cell. In subsequent cycles, the address increases, and the number of cycles decreases by one, until the contents of the number of cycles register (or rather, its 14 bits) becomes equal to zero. After that, a signal is generated end of countCOP and the following operating modes are possible:

• further increasing the address by adding one after the next cycle;
• blocking of the PDP channel ("КС-stop" mode);
• repetition of the previously selected array of addresses (autoload mode).

During the execution of the RAP cycles, three modes of operation are possible:

• mode reading,providing data transfer from memory to VU;
• mode records,providing data transfer from VU to memory;
• mode checks.In this mode, the DMA controller does not generate the signals ¯ChpP, ¯ZpP, ¯Rt and ¯Zp, which prevents the exchange of data between the memory and the WU. However, in each cycle, the DMA controller controls the system bus and confirms the WU requests. External devices can use acknowledgment signals to allow internal access to each byte in the data array to perform some verification operations. An array of check loops can follow an array of read loops to allow the VU to check newly arrived data.

The On-Board Flash Memory Controller (EFC) is part of the Memory Controller (MC) and provides an interface to access flash memory blocks over an internal 32-bit bus. This allows you to significantly increase the speed of fetching instructions from flash memory when the processor core is operating in Thumb mode (16-bit instruction system) due to the operation of a 32-bit buffer. What's more, the onboard flash controller supports a full set of commands for reading, writing, erasing flash, setting and unsetting protection bits.

20.2 Functional description

20.2.1 Organization of the built-in flash memory

The built-in flash memory interfaces are directly connected to the internal 32-bit bus, built around several of the following interfaces.

• Simple memory organization: multiple pages of the same size.
• Two 32-bit read buffers designed to increase the read speed of flash memory (see "Read commands" on page 101).
• One write buffer for storing data when programming one page of flash memory. This buffer is one page in size and can only be accessed for writing. In addition, the write buffer is used to address the flash memory in the entire 1 MB area (see "Write commands" on page 101).
• Multiple protection bits (lock bits) to prohibit erasing and writing of flash memory. Each protected area of \u200b\u200bflash memory (all areas are equal in size) consists of a fixed number of pages in sequence. Each one such area is directly associated with only one security bit.
• Several bits of non-volatile memory - NVM-bits (Non Volatile Memory) general purpose. Each of these bits is responsible for controlling specific nodes of the microcontroller. For more details on each NVM bit, see the corresponding chapters in this document.

The built-in flash memory size, page size, and protection bit organization are described in Chapter 9, Memory.

Table 20-1. Security and General Purpose NVM Bits for AT91SAM7S Family Members

Figure 20-1. Built-in flash memory map

20.2.2 Reading Commands

To speed up the flash reading process, a dedicated 32-bit buffer is built into the EFC. Due to the presence of this buffer, when the processor is operating in the Thumb mode (16-bit instruction system), the flash memory is accessed twice less frequently, due to which the instruction retrieval rate increases and, consequently, the processor's operating speed will increase (Fig. 20-2, fig. 20-3 and fig. 20-4).

This optimization is performed only when fetching instructions, and when reading data from flash memory, it is not performed.

Read commands can be executed both without including additional wait loops, or with them. Only up to three (inclusive) wait cycles can be set in the FWS (Flash Wait State) field of the MC_FMR flash mode register (see Flash Mode Register, page 110). With FWS \u003d 0, the internal flash memory is accessed in one cycle.

Flash memory can be accessed in 32-bit (dictionary), 16-bit (half-word) and 8-bit.

Since the size of the built-in flash memory is smaller than the microcontroller than the size of the address space of the internal memory allocated for it (1 MB), so-called. duplication of this block of flash memory across the entire address space allocated for it. For example, for AT91SAM7S64, 64KB flash memory is mapped in this address space exactly 1024/64 \u003d 16 times (translator's note).

Figure 20-2. Optimization when reading command code in Thumb mode for FWS \u003d 0

Figure 20-3. Optimization when reading command code in Thumb mode for FWS \u003d 1

Figure 20-4. Optimization when reading the command code in Thumb mode for FWS \u003d 3

20.2.3 Write Commands

The area of \u200b\u200bthe internal memory reserved for the built-in flash memory can also be written only through a special buffer. When executing write commands to flash memory, only the lower 8 bits of the address are taken into account (since it comes about 32-bit data, the least significant 10 bits of the address are actually taken into account). In turn, the upper 10 bits of the address of the internal area (1 MB), reserved for flash memory, address this so-called. a window whose size is 256 words (1024 bytes). This way, this whole inner memory consists of 1024 such windows.

Any write command to the built-in flash memory can be disabled using the Memory Protection Unit (MPU).

Writing to flash memory is possible only by dictionary (32 bits), so any attempt to write half words (16 bits) or bytes (8 bits) will cause an unpredictable result.

Write commands are executed in the number of wait cycles (FWS field in the MC_FMR register) specified for the read commands, plus one additional cycle, except when FWS \u003d 3 (see "Flash Memory Mode Register", page 110).

20.2.4 Flash Controller Command Set

The EFCS includes commands for programming flash memory, commands for setting protection (unprotecting) of its areas, commands for sequential programming and setting flash memory protection, a command for completely erasing the entire flash memory.

Table 20-2. Flash memory controller command set

Before executing any of these commands, the code of this command must be specified in the FCMD field of the MC_FCR register. Since access to the MC_FCR register is possible only by reading, the FRDY flag is automatically cleared. When the command finishes executing, the FRDY flag is automatically set, which can trigger the corresponding interrupt if enabled through the memory controller (MC).

All flash instructions are protected against accidental execution by a single common keyword, which must be specified in the upper 8 bits of the MC_FCR register each time a command is executed.

A command with an incorrectly specified keyword and / or an incorrectly specified command code will not be executed, even if the PROGE flag is set in the MC_FSR register. This flag will be automatically cleared the next time the MC_FSR register is read.

An attempt to execute a command to write or erase a page located in a protected area will not affect the contents of flash memory (in fact, this command will be ignored), even if the PROGE flag in the MC_FSR register is set. This flag will be automatically cleared the next time the MC_FSR register is read.

Figure 20-5. Flowchart of the command execution process

The Cycle Time in Microseconds (FMCN) field must be set to the correct value in the Flash Controller Mode Register (MC_FMR) for correct execution of Flash commands (see “Flash Controller Mode Register”, page 110).

20.2.4.1 Programming Flash Memory

Just a few commands can be used to program the flash memory.

According to the technology of the flash memory, it must be erased immediately before the process of its programming. Either the entire flash memory area can be erased, or separate page by clearing the NEBP flag in the MC_FMR register directly by writing the command code to the MC_FCR register.

When the NEBP flag is set in the MC_FMR register, the page can be programmed in a certain number of stages if it has already been cleared before that (see Fig. 20-6).

Figure 20-6. Example of programming a section of a flash page

After the end of the programming process, the page can be protected from accidental or intentional erasure or writing (when the entire area that this page belongs to is protected). With the WPL command, protection can be set automatically immediately after the end of the page write cycle.

The data to be written is stored in an internal buffer that is the size of one flash page. This internal buffer covers the entire address space of the internal flash memory, i.e. in fact, it can be entirely displayed on any of its pages.

Note: writing bytes (8 bits) or half words (16 bits) is prohibited, since how it distorts the recorded data.

The process of writing data to flash memory previously allocated in an internal buffer is controlled by the flash command register (MC_FCR). The sequence of work with this register is shown below.

• Writing the entire page, which can be located at any address within the entire address space of the flash memory, is possible only in dictionary (32-bit data).
• The page write cycle begins immediately after the number of this page and the write command code itself are indicated in the MC_FCR register. This automatically clears the FRDY flag in the Flash Programming Status Register (MC_FSR).
• Immediately after the completion of the programming cycle, the FRDY flag is set in the Flash Programming Status Register (MC_FSR). If interrupts from the FRDY flag are enabled, then the corresponding interrupt signal will occur in the memory controller (MC).
• Programming Error: An invalid was written to the MC_FSR register. keyword and / or an invalid command was specified.

20.2.4.2 Full erase flash command

All on-chip flash memory can be cleared if the Erase All (EA) command is written to the MC_FCR register.

Erasing the entire flash memory is possible only when none of its areas is protected against erasure and writing (none of the flash memory protection flags are set). Otherwise (at least one of the security flags is set) this command will be ignored. If the LOCKE flag is set in the MC_FMR register, then the corresponding interrupt signal will occur.

The FRDY flag will automatically be set in the MC_FSR register after the last programming command is executed or the flash is erased. In this case, the output of the memory controller (MC) will immediately generate a signal of the corresponding interrupt, if enabled.

During the execution of the programming cycle, errors may occur, which are recorded in the MC_FSR register. Below are these errors.

• Programming Error: An invalid keyword was written to MC_FSR and / or an invalid command was specified.
• Lock Error: An attempt was made to program a secure area. To perform correct programming of this area, its protection must first be unprotected using the unprotect command.

20.2.4.3 Flash Protection Bits

Each of the protection bits is tied to specific area flash memory consisting of a certain number of pages. The purpose of these bits is to protect the flash memory from accidental or intentional erasure / programming.

During the manufacturing process of the microcontroller, some of the protection bits may be set in it. Their purpose is to protect a certain area of \u200b\u200bthe flash memory, which by default contains the program written to the microcontroller during its production. Before programming / erasing a protected area, its protection must be removed.

The following is the sequence for setting up one area protection:

The following value must be written to the flash memory command register: (0x5A after the protection command is completed, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately occur at the output of the memory controller (MC), if enabled. Ul\u003e

After installing the protection, it can be removed, below is the sequence for removing the protection of one area:

• the following value must be written to the flash memory command register: (0x5A after the protection command is completed, the FRDY flag in the MC_FSR register will be set. In this case, the corresponding interrupt signal will immediately appear at the output of the memory controller (MC), if enabled.

If an error occurs during the execution of a command (an incorrect keyword and / or an incorrect command code is specified in the MC_FCR register), this fact will be recorded in the MC_FSR register.

The execution of the command to clear the protection bit physically writes "1" to the corresponding bit, although when the MC_FSR register is read, the corresponding LOCKx bit is read as "0". Conversely, executing the command to set the protection bit physically writes "0" to the corresponding bit, and when reading the MC_FSR register, the corresponding LOCKx bit is read as "1".

Note: regardless of whether flash memory is protected, it is still readable.

20.2.4.4 General Purpose NVM Bits

General Purpose Bits - NVM Bits - are not associated with the on-board flash memory, but are intended to protect other parts of the microcontroller. Each of these bits can be set (cleared) independently of the others. For details on NVM bits, see the relevant chapters in this document.

Below is the sequence for activating general purpose NVM bits.

• Executing the Set General Purpose NVM Bit (SGPB) command by writing this command code and the number of these bits in the PAGEN field of the same register to the Flash Command Register (MC_FCR).
• when the SGPB command completes, the FRDY flag will be set in the MC_FSR register. In this case, the output of the memory controller (MC) will immediately generate a signal of the corresponding interrupt, if enabled.

During the execution of the programming cycle, errors may occur, which are recorded in the MC_FSR register. Below are these errors.

• The PAGEN field of the MC_FCR register specifies the number of general-purpose bits greater than the maximum number of NVM bits implemented in the die. Below is the sequence for clearing general purpose NVM bits.
• Executing the Clear General Purpose NVM Bit (CGPB) command by writing the code of this command and the number of these bits in the PAGEN field of the same register to the Flash Command Register (MC_FCR).
• when the CGPB command completes, the FRDY flag in the MC_FSR register will be set. In this case, the output of the memory controller (MC) will immediately generate a signal of the corresponding interrupt, if enabled.

During the execution of the programming cycle, errors may occur, which are recorded in the MC_FSR register. Below are these errors.

• Programming error: An invalid keyword was written to the MC_FSR register and / or an invalid command was specified.
• The PAGEN field of the MC_FCR register specifies the number of general-purpose bits greater than the maximum number of NVM bits implemented in the die.

Executing the "Clear General Purpose NVM Bits" command physically writes "1" to the corresponding bit, although reading the MC_FSR register reads the corresponding bit of GPNVMx as "0". Conversely, executing the command "set general purpose NVM bits" physically writes "0" to the corresponding bit, and when reading the MC_FSR register, the corresponding bit of GPNVMx reads "1".

Note: Regardless of the state of the general-purpose NVM bits, read access to the flash memory is always possible.

20.2.4.5 Privacy bit

The security bit is intended to prevent external attempts to access the internal system bus. Once the privacy bit is set, the JTAG interface, flash programming interface, and serial access to flash memory are prohibited. Access to the flash memory via the above interfaces is only allowed again when complete cleaning crystal on external pin ERASE - see chapter 4. "Pin assignment". When a high logic level is applied to the ERASE pin (see clause 7.4. "Erasure control output"), all flash memory implemented on the chip, all flash memory protection bits, all general-purpose NVM bits are cleared, and only after all this is done clearing the privacy bit.

The sequence for setting the privacy bit is shown below.

• Executing the Set Security Bit (SSB) command by writing the command code to the Flash Command Register (MC_FCR).
• when the SSB command completes, the FRDY flag in the MC_FSR register will be set. In this case, the output of the memory controller (MC) will immediately generate a signal of the corresponding interrupt, if enabled.

As soon as the security bit is set, the SECURITY flag will be set in the MC_FSR register.

Controller functions dynamic memory:

Conversion of MP commands into a sequence of special signals that provide writing / reading to the dynamic memory module.

Providing a mode of regeneration of the dynamic memory module.

Securing heap accesses.

The controller manages four DRAM modules. The cycle time of memory access is reduced. Total capacity of 4 modules \u003d 1 MB * 32 bit words \u003d 4 MB. 22 bits of the address are used:

А0 А1 - used for internal use of the MP. Determine the used byte, are not issued outside.

BE3. ... ... BE0 - byte enable

A3 A2 - provide lamination

A21 A4 - to addressable module inputs

Since the memory is built on four memory modules, the controller must generate four pairs of strobe signals.

M0 M1 ... M3

9 bits of the address must be formed by the controller and issued in parts

The write signal WE - write enable must be generated

DEN - data enable

The memory module connects directly to the processor line.

MP status signals:

- signal activating the controller microcircuit

CLK - according to this signal, all changes in the microcircuit occur

Consider the interaction of the MP, the controller and the dynamic memory block

1. Dram controller (kdp)

Cache memory

Currently, a two-level cache is being organized: internal (cache1), external (cache2). The cache is built on static memory - SRAM. There is a memory cache controller.

1. External cache characteristics

Capacities up to 512KB

High performance (provided by using SRAM)

Information is stored in blocks. Block is a set of contiguous bytes (4 ... 64 bytes). The block is usually much longer than the word.

Types of cache:

associative cache - associative cache

direct mapped cache - direct mapped cache

two way associative cache - two-way associative cache

1. Cache controller functions

Physical address analysis... If fixed CACH - hit on reading, the required information enters the processor from the cache. If happened CACH - read miss, then the information is extracted from the OP. With CACHE - hit on record, the current result is entered into the cache. With CACHE - write miss, the response of the cache controller may differ depending on the type of cache used:

end-to-end recording - recording is performed in the OP.

writeback - writing is done to the cache. The modified information gets into the OP when it is unloaded from the cache.

Snooping -Eavesdropping bus addresses. The cache monitors the change in the contents of the memory, initiated by the IP. All calls to the OP, with a two-tier organization, go through the cache. The first call goes to the cache. If a change to the contents of the OP is initiated by another master, the cache is not aware of these changes. There is a mismatch between the information stored in the RAM and in the cache. Address bus eavesdropping is used to avoid this. If the controller detects that an address is being addressed, a copy of the contents of which is stored in the cache, the corresponding cell in the cache is declared invalid.

Cache directory support... Support for the implementation of the principles of displaying information from the OP in the cache.

Sometimes, when developing a device, there is a need to save some data to non-volatile memory. In such cases, the internal EEPROM of the microcontroller is usually used. If it is not enough, then, as a rule, external EEPROM chips from the 24lxx series are used. Microcircuits of this series are very popular. Most often they can be found in old mobile phonessome motherboards, cartridges from printers and many more where. The price of these microcircuits is also very attractive. For example, 24LC16 costs 11 rubles.
This microcircuit is produced in different buildingsthe most popular of which are DIP and SOIC. The microcircuit has the following pinout:

As you can see, there are very few conclusions. So let's try to figure out what's what.
A0, A1, A2 - are not used in this microcircuit. They can be connected to ground or to positive power. In some other microcircuits of the 24lxx series, these pins can set the address of the microcircuit, so that 8 microchips of memory can be connected to one i2c bus at once.
Vss - Earth.
SDA - data line
SCL - clock line
WP - Write protection. When this pin is logical 0, then writing to memory is allowed. If you give a logical unit, then only reading from memory is possible.
Vcc - microcircuit power supply. According to the datasheet, it is powered by a voltage of 2.5 volts to 5.5 volts.

Connection to the controller.
It is very easy to connect memory to MK. From the harness, only a pair of resistors with a resistance of about 4.7 kOhm are required.

Software

To work with memory, a library was developed that implements the following functions:

i2c_init - adjusts the speed of clock pulses going along the line SCL.

The 24LC16 chip supports frequencies up to 400 kHz. You can calculate the frequency like this:

CPU Clock frequency - the frequency at which the microcontroller operates

TWBR - the number written in the register of the same name.

TWPS Is a prescaler. The prescaler values \u200b\u200bare set by the TWPS1 and TWPS0 bits in the TWSR register.

For the Atmega 32 controller, the following table is valid:

i2c_start- sends the starting package

i2c_stop - sends a stop message

i2c_send- sends a byte

i2c_recive - takes a byte

i2c_recive_last- takes the last byte. The difference from the previous function is that when a byte is received, the microcontroller does not send a confirmation bit. If, when receiving the last byte, use i2c_recivethen the SDA line will remain pressed to the ground.

Writing data to a memory chip

You can write data both in random order and page by page. Since there can be several devices on the i2c bus at once, in order to address any device, you need to know its seven-bit address. The binary address of the 24LC16 chip looks like this:

Bits A, B, C are used to select a memory block. There are 8 memory blocks in the microcircuit, 256 bytes each. Correspondingly, the ABC bits take values \u200b\u200bfrom 000 to 111.

In order to write a byte to the microcircuit, you need to perform the following sequence of actions:

1. Initialize i2c interface
2. Send starter package
3. Send microcircuit address + memory block address
4. Send the address of the memory cell to which the recording will be made
5. Send data byte
6. Send stop parcel

Example: Need to write a byte 0xFA by the address 0x101.

rcall i2c_init
rcall i2c_start
ldi temp, 0b 1010 001 0 // Chip address where:
// 1010 - microcircuit address
// 001 - memory block address (Cell 0x101 belongs to block 1)
// 0
rcall i2c_send
ldi temp, 1 // Address of the memory location. (block 1, cell 1)
rcall i2c_send
ldi temp, 0xFA // Load the bytes to be written into the register
rcall i2c_send // Write byte
rcall i2c_stop

You can write data to memory not only byte-by-byte, but also page-by-page. The page size is 16 bytes. Per-byte writing implies the following: We send the address of the zero byte of the desired page and then send the required data 16 times. The address counter will be incremented by one automatically. If you send data for the 17th time, a zero byte will be overwritten, if you send a byte for the 18th time, it will overwrite byte number 1, etc.

Example: It is required to write the first page of block 0.

rcall i2c_init // Initialize the i2c interface
rcall i2c_start // Send the starting package
ldi temp, 0b 1010 000 0 // Chip address where:
// 1010 - microcircuit address
// 000 - memory block address (we are interested in the zero block)
// 0 - read / write bit. 0 - write, 1 - read
rcall i2c_send
ldi temp, 16 // Address of the first page
rcall i2c_send
ldi temp, 0x01 // Load byte number 0 into the register
rcall i2c_send // Write byte
ldi temp, 0x02 // Load byte number 1 into register
rcall i2c_send // Write byte
/// here we write the rest of the bytes .....
ldi temp, 0x0E // Load byte number 14 into register
rcall i2c_send // Write byte
ldi temp, 0x0F // Load byte number 15 into register
rcall i2c_send // Write byte
rcall i2c_stop // Send a stop parcel

Reading data from a microcircuit
We sort of figured out the recording, now let's start reading. To read a byte, you need to do the following:

1. Initialize the i2c interface (if it hasn't been initialized earlier)
2. Send starter package
3. Send the address of the microcircuit and the address of the memory block from where we will read
4. Send memory address
5. Resend the starter package
6. Send the address of the microcircuit and the address of the memory block with the "read" bit
7. Get byte
8. Send Stop Parcel

rcall i2c_init // Initialize the i2c interface
rcall i2c_start // Send the starting package
ldi temp, 0b1010 011 0 // Chip address + address of the 3rd memory block.
// Read / write bit is still 0!
rcall i2c_send
ldi temp, 0x41 // Address of the memory location
rcall i2c_send
rcall i2c_start // Resend the starting package
ldi temp, 0b1010 011 1 // Chip address + memory block address + read / write bit became 1
rcall i2c_send // now you can read data
rcall i2c_recive_last // Read a byte. First and last.
rcall i2c_stop // Send a stop parcel

Reading can be performed sequentially byte by byte, i.e. just calli2c_recive As much as needs. There is no need to send the command to increment the address by one. It is also not necessary to switch block addresses during sequential reading. Those. you can take and read the entire microcircuit at once without any problems.

The library for working with i2c was developed and tested on the Atmega32 microcontroller. I think it will work on many other controllers without any changes. Naturally, the controller must have hardware support for i2c, or as it is also called TWI. Of course, you can implement i2c programmatically, but I didn't bother and there was no need. The demo example is a program that writes bytes from 0 to 15 to the first 16 addresses, and after writing it outputs them to port A. You can watch how this works not only live, but also in Proteus.

And finally, I attach an oscillogram:

This is what the i2c bus looks like through my eyes :-)
All questions and suggestions are waiting in the comments.